Please refer to FIG. 1, which illustrates the conventional phase locked loop (PLL) circuit. The PLL circuit 100 includes a phase frequency detector 10, a charge pump 20, a loop filter 30, a voltage controlled oscillator (VCO) 40 and a divider 50. An input clock signal (CKin) with a reference frequency (fref) is generated by a reference oscillator (not illustrated). Both the input clock signal and a frequency divided signal are inputted into the phase frequency detector 10. The phase frequency detector 10 detects the difference in phase and frequency between the input clock signal (CKin) and the frequency divided signal and then outputs a phase difference signal to the charge pump 20. According to the phase difference signal, the charge pump 20 then outputs the current proportional to the amplitude of the phase difference. The output current charges capacitors C1 and C2 of the loop filter 30, thereby generates a control voltage (Vc) to the VCO 40. The VCO 40 generates an output clock signal (CKout) with a voltage controlled frequency (fvco) in response to the control voltage (Vc). The divider 50 receives the output clock signal (CKout) and generates a frequency divided signal after dividing the voltage controlled frequency (fvco) by an integer M (i.e. multiply by 1/M) for being inputted to the phase frequency detector 10. Therefore, the frequency relation between input clock signal (CKin) and the output clock signal (CKout) of the PLL circuit 100 is fvoc=M*fref.
As widely known, the frequency operation range of the VCO 40 is restricted in its resonant frequency; further, the control voltage (Vc) is proportional to the voltage controlled frequency (fvco); hence, the control voltage (Vc) would be restricted within a voltage operation range. That is to say, the conventional frequency locked range of the PLL circuit 100 would be restricted to within the frequency operation range of the VCO 40.
In order to achieve PLL circuit with wide-locking range, as illustrated in FIG. 2, a PLL circuit with multi-modulus divider is proposed. The proposed multi-modulus divider 60 of the PLL circuit 150 includes a main divider 62 and a coefficient-selecting unit 64. The main divider 62 provides a basic numeric M. The coefficient-selecting unit 64 switches using the controlling pins to choose one of the coefficients from many (1, ½, ¼, . . . , ½N). For example, if user selects the coefficient ½ from the coefficient-selecting unit 64, the output voltage controlled clock signal (CKvco) with a voltage controlled frequency (fvco) outputted from the VCO 40 is undergoing a first frequency division by the coefficient ½ to generate the output clock signal (CKout) with an output frequency equal to fvco/2. The output clock signal (CKout) further undergoes a second frequency division by the main divider 62 according to the basic numeric M, which divides the output frequency (fout) of the output clock signal (CKout) by the integer M (multiply by 1/M) to generate the frequency divided signal with frequency equal to fvco/2M.
The conventional multi-modulus divider 60 provides a coefficient-selecting unit 64 to the PLL circuit 150. Through dynamically selecting one value of the coefficient-selecting unit 64 and applying to the PLL circuit 150, the output frequency (fout) of output clock signal (CKout) can achieve the purpose of wide-locking range. However, when designing such kind of PLL circuit in an application specific integrated circuit (‘ASIC’), a set of control pins are needed to be provided additionally in order to control switches (SW0˜SWN) and select one coefficient in the coefficient-selecting unit 64 by user. The additional control pins or terminals would however increase difficulty of operation and the cost and complexity of design and testing.